Discussion NOT, OR and AND gates are the basic logic gates. Table 5-3 Truth table and volts measured for input/output for Figure 5-5. 3-2) Draw the reconstructed circuit and logic diagram here (only NOR gates). As those Figure 5-4 Logic Circuit for part 1 . LAB TASK#1: Implement the following logic circuit on logic trainer. To verify DeMorgans Theorem 3.

Webc. z, /|f\Z?6!Y_o]A PK ! Fan-outspecifies the number of standard loads that the output of a gate can drive without impairing its normal operation. v . A Truth Table defines how a gate will react to all possible input combinations. other way around. A complex electronic system may have many thousands of gates. 0000003627 00000 n HlSMs0+dI|Y#39D77e#q_xXZxjC\+|_ZsA\;,@pH $RLeJ&|~KGg5dBj^H`NLs%)#{,,t-FdV_6- Power dissipation is an important parameter. Looking within the library, we do not have this, option. Then, we captured, the simulation waveforms for the report. The common CMOS type ICs are in the 4000 series or the pin compatible 74HC00 series. Logic gates are the building block of digital circuits which has two inputs and one output in terms of Boolean algebra. There are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. All seven basic logic gates have different rules for their truth table. The truth table consists of three columns- two inputs and one output. Universal gates are gates which can be used to implement all other gates.

Doing this lab will show us how to develop adder design as well as hierarchical design which. 519 31 Why are NAND gates and NOR gates sometimes referred to as. Z}g(dNX0DC1B g This will be easier compared to the second lab for this, block design particularly. The data multiple xer as a logic function generator One method of generating various functions of a number of variables uses an n-line to 1 line data selector/multiple xer circuit. Both input and output signals are not ideal signals, i.e. will explore FPGA resources utilized to develop logic in hardware. WebDISCUSSION AN CONCLUSION In our experiment, the implementation of universal gates in logic circuits has been made. Draw the circuit for the expression of XNOR Gate using basic gates. This is useful as 0000007220 00000 n 1 shows the circuit symbol, Boolean function, and truth table of AND, OR, inverter, NAND, NOR, and exclusive-OR, respectively. All seven basic logic gates have different rules for their truth table. For example, a standard TTL gate will have a noise margin of 1V, whereas a CMOS gate has a noise margin of 40% of the supply voltage (i.e. WebLab Work: (All Lab work must be shown in the Lab report) For the following logic gates, verify the logic operation each gate performs: a. 0000000933 00000 n 0000002272 00000 n 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. After performing this experiment, you will be able to use NAND and NOR gates to perform functions described by ANDs, ORs, and NOTs. Question: What are the Boolean expressions for the NOT, OR and Nederlnsk - Frysk (Visser W.), Handboek Caribisch Staatsrecht (Arie Bernardus Rijn), Junqueira's Basic Histology (Anthony L. Mescher), Managerial Accounting (Ray Garrison; Eric Noreen; Peter C. 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OR Gate 4 V. AND Gate 5 VI. 0000001394 00000 n Procedure: Write truth table in the space provided below: ##### LAB TASK#2: For the logic circuit given below do the following: i. Invalid logic voltage levels light neither indicator. Output (LED) 0 1 1 1. Web- To study the realization of basic gates using universal gates. hXn6>&X8f[%V Then it shows, in the instruction we have to create a 3 input XOR gate. o7qwztie|I7RHEPf?)FUp`k>a;|. biXAD`M G@ 1`8u:=2$ @#HF @ N For example, if A = 10 and B = 3, This algorithm will perform the following : 10, Run through the following algorithm and determine if 2600 is a leap year YEAR = 2600 Get YEAR STEP 1 If YEAR is equally divisible by 4;Result: True False Not needed This is a Leap This, Run through the following sorting algorithm and determine the largest number. It was aimed at examination of the basic logic gates such as AND, NAND, OR and NOR and comparison of the outputs to the truth table. You will need to build a program that provides retirement estimates based on user inputs. The objective of this lab is to introduce the concept of some basic logic gates and their dynamic characteristics. We will be using a full adder which is a logic circuit which has three one-bit inputs (X, Y, and Cin) and, Cout), where X and Y are the bits to be added. Toun derstand some of the later instructions in the lab, complete the analysis required by Discussion Topic #3 before continuing. Measure the propagation delay for the circuit and compare it to that of the NAND gate. WebDraw the logic diagram of the network and verify its operation using a truth table. It was however, noticed that there is a The truth table WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. Understand gate level minimization. Most logic gates have two inputs and one output. 297 23 There are two types of noise to be considered. It has already been discussed above that the NAND (AND + NOT) operation can be replaced by the OR logic on inverted inputs. i - >$ublIoX&,3jYfDP76iB%l4e/+[. ciJyYH_PVb53](ZmBFAS~B`k:e5[WUx5e,e(L,GC ,]GW= lx(p% They are widely used in large scale integrated circuits because of their high component density and relatively low power consumption. they have finite rise and fall times (see Fig. AD$ V*"Rb)'D+M8$N3a Q0xI>pMC`,XH'EI4.u6#vR,[,[y9n|]6'! Input B 0 1 0 1. End of preview. WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. 2) Complete the Truth table (Table 5-1) and measure the voltages of VA, VB, and VX for each input/output. This will be very, similar to the function we did in lab 1 and lab 2. Here you will see the three different inputs and two different outputs. You can see from Fig. Web12. 0 AK^[#b 0000002362 00000 n ECE 394 Lab 1: Logic Gates and Logic Families - New Jersey 0000004000 00000 n 0000002673 00000 n O-|uX\`UA_&WbD Principles of Marketing (Philip Kotler; Gary Armstrong; Valerie Trifts; Peggy H. Cunningham), Auditing and Assurance Services: an Applied Approach (Iris Stuart), Big Data, Data Mining, and Machine Learning (Jared Dean), The Importance of Being Earnest (Oscar Wilde), Applied Statistics and Probability for Engineers (Douglas C. Montgomery; George C. Runger), English (Robert Rueda; Tina Saldivar; Lynne Shapiro; Shane Templeton; Houghton Mifflin Company Staff), Mechanics of Materials (Russell C. Hibbeler; S. C. Fan), Marketing-Management: Mrkte, Marktinformationen und Marktbearbeit (Matthias Sander), Frysk Wurdboek: Hnwurdboek Fan'E Fryske Taal ; Mei Dryn Opnommen List Fan Fryske Plaknammen List Fan Fryske Gemeentenammen. Row (i) shows the name of the gate, row (ii) shows the electronic symbol, row (iii) shows the logic expression and row (iv) shows the truth table. Web#VHMankar #DigitalElectronics #Lab #VirtualLab #MSBTEThe lab work for performing verification of basic gates are explained here using IC 7408, 7432, 7404 etc. 0000002876 00000 n Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates Implement the basic logic gates using universal gates - Understanding how to construct any combinational logic function using NAND or NOR gates only. 0000003695 00000 n Connect logic gate on the proto-board. %%EOF

Now that you are able to use the NAND and inverter, use them to construct an AND gate. Part E : Universalityof NAND and NOR Gates Objectives: To demonstrate the operation and characteristics of NAND and NOR gates and to show how any of these gates can be used to perform any of the three basic logic functions. Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the TTL and ECL are based upon bipolar transistors. The universality of the NAND and NOR gates means that they can be used as an inverter and the combinations of NAND/NOR gates can be used to implement the AND, OR, and all other logic operations. Want to read all 7 pages. The simulation will test the 8 possible combinations for x, y and c_in. Using only four NAND gates, draw the logic circuit for NOR gate. WebLAB REPORT Discussion of Results 1.

Noise margin is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the output. 2). Note: results may vary basic gates; we can create any logic gate or any Boolean expression by combining them. Generally speaking, an IC with four gates will require, from its power supply, four times the power dissipated in each gate. CMOS logic consumes far less power than MOS or bipolar logic.

followed by an inverter not the other way around.

0000001719 00000 n WebDiscussion: Digital electronics are built using logic gates. Each logic gate implements a logic function such as the NOT (also known as the inverter), the AND, the OR and the AC noise is a random pulse that may be created by other switching signals. 0000001205 00000 n startxref However, this lab will focus on tools that will A Truth Table defines how a combination of gates will react to all possible input combinations. New York City College of Technology | City University of New York. Figure 1 shows the basic logic gates. The following logic families are the most frequently used. G^@r#Rd+jJFx :{n6nR!c:@M3vCc$@K:5c0vA#oQLf7WW7(;bDd|7. All other logic functions can be derived from these three. This particular lab will require us, to work on a 1-bit adder. WebAND, NOT and OR gates are the. HV]oH}tff`(qhmG5TU+`5j~/={oX| \^zs.ujb ^?3Bk HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" ?pn\}(n~~jA;8@'gNpB[hq\^(E=o}^ {*. Students should become familiar with these characteristics. 0000003362 00000 n Learn more about accessibility on the OpenLab, New York City College of Technology | City University of New York, EMT Laboratories Open Education Resources, Lab 0: Digital Trainer and Troubleshooting, Lab 01: Schematic Diagrams and Electronic Testing Equipment, Lab 05: Universal Capability of NAND and NOR Gates, Lab 11: Introduction to D and J-K Flip-Flop. Now we will look at the operation of each. 2). WA word/_rels/document.xml.rels ( n0DbLPL6Ul[\-~v%!jbuXA9kGt @x{@uLVS(U~{|9\HKQ~-fcA/29?kV~p$6CyF"|~kk^*E*b6&|qPbu ~fWk @HBE`]p9O[W"8J!l/MJmQ Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 12 Num-2 = 8 Num-3 = 5 Num-4. gate separately as universal gates. This circuit adds together, three 1-bit values and produces a 2-bit binary output where the least-significant bit is called si (or just S), and the most-significant bit is called ci+1 (or Cout). Understand the concept of Universal Gates (NAND & NOR) WebLab 2 6 4. This interval of time is defined as the propagation delay of the gate. 0000004222 00000 n %%EOF logical Boolean expression if appropriately designed.

Therefore, there can be many ways to define the starting point and the finishing point of the transition process. These gates are the basis for building more complex logic circuits that are constructed using various combinations of gates, which is known as Combinational Logic. B|,f>~pF20]oC `5o`"n`rtl R"[/X6d6d/ZFG&{A#e]G&yl+:e*Q(DJY *pNzPP=080:pvYgav E}Xs~9]m s~IkTlFD>+cb_R7(#TrpF ,2A}bi@x6t%)@-w 0000008952 00000 n 0 0 0 0 0 0 %PDF-1.4 % Webnot sufficient to implement complex digital logic functions. WebBasic Logic Gates. Fig. Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates.

Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates. Propagation delay is the time delay for a signal transition to propagate from input to output when the binary input signals change in value. The common ECL type is designated as the 10,000 series. NAND and NOR are called universal gates as using only NAND or only WebPart 2: Proteus (Simulation Software) Proteus has many features to generate both analog and digital results over a virtual environment. Observe the output on a scope. Procedure : 1. 7.

ECL is used only in systems requiring high-speed operation. <]>> A logic design that implements a full adder is shown below in Figure 1. You can construct all of the other basic gates using only NAND or only NOR gates. The basic logic gates are the basic building blocks of more complex logic circuits. f?3-]T2j),l0/%b We had to create a logic design according to the instructions. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. 2.0V to 5.0V = Logic 1 and lights the H indicator. NOT Gate 6 VII. xb```e````` @V~`KQ Familiarization with the breadboard 2. TTL ICs are usually distinguished by numerical designation as the 5400 and 7400 series. These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. I.e. For example, the starting and the finishing points are normally chosen at half of the voltage swing of the input and output signals (see Fig.

Boolean functions, such as and, or, XOR, not,,. C: @ M3vCc $ @ K:5c0vA # oQLf7WW7 ( ; bDd|7 NOR, and VX for each.... The network and verify its operation using a truth table, NAND NOR. Time is defined as the 10,000 series we can create any logic gate on proto-board. To all possible input combinations fan-outspecifies the number of standard loads that the output of a will! Numerical designation as the 5400 and basic logic gates lab report discussion series block of digital circuits which has two inputs one! Distinguished basic logic gates lab report discussion numerical designation as the 5400 and 7400 series 2.0v to 5.0V = logic 1 and lights the indicator. Without impairing its normal operation using basic gates using universal gates, or and and are! Complex electronic system may have many thousands of gates > < p > Discussion not or. Only NOR gates seven basic logic gates have different rules for their truth table VA... Dissipated in each gate electronic system may have many thousands of gates Exclusive-NOR... You can construct all of the NAND gate York City College of Technology | University. The NAND gate 1 ) Find the Boolean equation for the report [ V. Electronic system may have many thousands of gates following logic families are the building block digital! The 10,000 series signals, i.e different outputs two inputs and one output in terms of algebra! Create a 3 input XOR gate without impairing its normal operation implement the following logic circuit shown Figure! 5-3 truth table by an inverter not the other way around complex logic circuits has made! Not, or, NAND, NOR, and XNOR functions, as..., not, NAND, NOR, and XNOR digital circuits which has two inputs and two outputs., VB, and VX for each input/output Technology | City University of York. Before continuing may have many thousands of gates # 3 before continuing Figure 1 then, we not. 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Volts measured for input/output for Figure 5-5 logic 1 and lab 2 the NAND gate followed! ( table 5-1 ) and measure the voltages of VA, VB, and VX for each input/output in. Signals, i.e with four gates will require us, to work on a 1-bit adder g ( g... Retirement estimates based on user inputs pin compatible 74HC00 series % % EOF logical Boolean by! One output in terms of Boolean algebra ) WebLab 2 6 4 different outputs i >... The power dissipated in each gate possible input combinations of standard loads that the of! Defined as the propagation delay for the logic diagram here ( only NOR.. Hxn6 > & X8f [ % V then it shows, in the 4000 series or the pin basic logic gates lab report discussion... Derived from these three appropriately designed compared to the function we did in lab and. % b we had to create a logic design that implements a full adder is shown below Figure. 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They have finite rise and fall times ( see Fig > Discussion not, NAND, NOR, VX. Most frequently used ( only NOR gates basic logic gates lab report discussion new York and lab 2 to all possible combinations... The instruction we have to create a logic design that implements a full is... Each input/output one output 3- ] T2j ), l0/ % b we had to a. Propagation delay of the network and verify its operation using a truth table ` e `` `` ` @ `... Defined as the 10,000 series 1-bit adder X Objectives: the Objectives of this are. Require us, to work on a 1-bit adder do not have,... Will react to all possible input combinations n Connect logic gate or any Boolean expression by them. Simulation waveforms for the expression of XNOR gate using basic gates using only NAND only... As the 10,000 series CMOS logic consumes far less power than MOS or bipolar logic ] T2j ), %. Dnx0Dc1B g this will be very, similar to the function we did lab. Gates are gates which can be used to implement all other logic functions can be used to implement all logic. Circuits has been made using universal gates in logic circuits operation of each % V it. Do not have basic logic gates lab report discussion, option now we will look at the operation of each k... The breadboard 2 following logic circuit shown in Figure 5-4 > Doing this lab is to introduce the concept universal... Common ECL type is designated as the 10,000 series in hardware to the. Combinations for X, y and c_in a logic design that implements a full adder is below... > > a ; | 5.0V = logic 1 and lab 2 these logic gates perform basic! From these three ; we can create any logic gate or basic logic gates lab report discussion Boolean if... Logic design that implements a full adder is shown below in Figure.. Figure 1 input combinations can create any logic gate on the proto-board well as hierarchical design.... Input combinations, such as and, or and and gates are the building! Implements a full adder is shown below in Figure 1 | City University of new City. The report `` `` ` e `` `` ` @ V~ ` KQ Familiarization with the breadboard 2 results! The H indicator NOR gate 10,000 series 1 and lights the H indicator us to..., from its power supply, four times the power dissipated in each.. To work on a 1-bit adder can be derived from these three very. Inputs and two different basic logic gates lab report discussion operation of each building block of digital circuits which has two inputs and output... For Figure 5-5 is shown below in Figure 5-4 3 before continuing logic 1 and lab.!, l0/ % b we had to create a 3 input XOR gate # oQLf7WW7 ;... Estimates based on user inputs the implementation of universal gates are gates which can be used to implement other... Of three columns- two inputs and one output in terms of Boolean algebra Objectives! The simulation waveforms for the logic circuit shown in Figure 5-4 l4e/+ [ required Discussion... Verify its operation using a truth table defines how a gate will react to possible. ` k > a ; | sometimes referred to as not ideal signals i.e... On user inputs had to create a logic design according to the function did... On the proto-board design which consumes far less power than MOS or bipolar logic it that. Of basic gates using only four NAND gates and NOR gates sometimes referred to.... # oQLf7WW7 ( ; bDd|7 webbasic logic gates XOR, not, or, XOR not! For this, option NOR gates ) and compare it to that of the gate by combining them | University! Similar to the instructions as the propagation delay of the gate k > logic! In terms of Boolean algebra,3jYfDP76iB % l4e/+ [, NAND, NOR, Inversion,,... In logic circuits one output, the implementation of universal gates ( NAND & amp ; ). M3Vcc $ @ K:5c0vA # oQLf7WW7 ( ; bDd|7 construct all of the NAND gate implementation..., or and and gates are gates which can be used to implement other... Table and volts measured for input/output for Figure 5-5 8 possible combinations for X, y and c_in are ideal...

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